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Host Controller Interface FW323 06 1394a

Discussion in 'Repair Laptop' started by bga, Apr 11, 2015.

Host Controller Interface FW323 06 1394a 5 5 1votes
5/5, 1 vote

  1. #1 bga, Apr 11, 2015
    Last edited by a moderator: Nov 20, 2016
    FW323 06 1394a PCI PHY/Link Open Host Controller Interface

    - Three fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic
    - Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders
    - While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving
    incoming bias voltage on that port
    - Does not require external filter capacitor for PLL
    - Supports link-on as a part of the internal PHY core-link interface
    - 25 MHz crystal oscillator and internal PLL provide a 50 MHz internal link-layer controller clock as well as
    transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s
    - Interoperable across 1394 cable with 1394 physical layers (PHY core) using 5 V supplies
    - Provides node power-class information signaling for system power management
    - Supports ack-accelerated arbitration and fly-by concatenation
    - Supports arbitrated short bus reset to improve utilization of the bus
    - Fully supports suspend/resume
    - Supports connection debounce
    - Supports multispeed packet concatenation
    - Supports PHY pinging and remote PHY access packets
    - Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V

    - 128-pin TQFP lead-free package
    - 1394a-2000 OHCI link and PHY core function in a single device:
    - Single-chip link and PHY enable smaller, simpler, more efficient motherboard and add-in card designs
    - Enables lower system costs Leverages proven 1394a-2000 PHY core design
    - Demonstrated compatibility with current Microsoft Windows® drivers and common applications
    - Demonstrated interoperability with existing, as well as older, 1394 consumer electronics and peripherals
    - Feature-rich implementation for high performance in common applications
    - Supports low-power system designs (CMOS implementation, power management features)
    - Provides LPS, LKON, and CNA outputs to support legacy power management implementations


    - Complies with the 1394 OHCI 1.1 Specification
    - OHCI 1.0 backwards compatible—configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode Complies with Microsoft Windows logo program system and device requirements
    - Listed on Windows hardware compatibility list Compatible with Microsoft Windows and MacOS
    operating systems.
    - 4 Kbyte isochronous transmit FIFO
    - 2 Kbyte asynchronous transmit FIFO
    - 4 Kbyte isochronous receive FIFO
    - 2 Kbyte asynchronous receive FIFO
    - Dedicated asynchronous and isochronous descriptorbased DMA engines
    - Eight isochronous transmit contexts
    - Eight isochronous receive contexts
    - Prefetches isochronous transmit data
    - Supports posted write transactions
    - Supports parallel processing of incoming physical read and write requests
    - Supports notification (via interrupt) of a failed register access
    - May be used without an EEPROM when the system BIOS is programmed with the EEPROM contents.

    1394a-2000 PHY core:

    - Compliant with IEEE 1394a-2000, Standard for a
    High Performance Serial Bus (Supplement)

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